The present invention pertains to digital signal processors and more particularly to floating-point systolic arrays including digital signal processors.
The basic systolic structure is a two-dimensional array of processing elements in which each processor communicates directly with its nearest neighbors. This structure performs well on algorithms with strong locality of signal flow. There are at least two forms of systolic array architectures. One form has relatively fewer processing elements, and each processing element is individually programmable. This can make software development difficult. Another form has every processing element performing the exact same operation on its local data. The entire array is programmed simultaneously. This offers the advantage of reduced software development. However, it complicates data-based decision branching since each element is operating on different data.
A prior art systolic array chip, identified by the number NC45CG72 is commercially available from NEC Corp. of Japan. The NC45CG72 systolic array is based on a 6 by 12 array of 1 bit processing elements. Each processing element contains a full add/subtract ALU and a 128 bit RAM. Also, the 72 element chips are cascadable into larger arrays. A 32 bit floating-point benchmark written for this chip indicates an execution time of 171 microseconds.